CPU96


8 registers
PC,A,S,P,W,X,Y,Z
Four addressing modes:
Instructions in the last three categories have one 16 bit parameter.
more info coming soon.
rrr selects a register.
iii selects either an index register for addressing or an second
register 
operand, depending on addressing mode, selected by mm:

mm=0: register  (eg txa           )
mm=1: immediate (eg lda #$nnnn    )
mm=2: indexed   (eg lda  $nnnn,x  )
mm=3: indirect  (eg lda ($nnnn),z )

To get absolute addressing, link cleverly and use PC as the index
register,
or use a zero index.
Perhaps address indexing should be disabled if PC is selected as the
index???

Instruction set:

0000 rrr 0000 mm iii  + adc    mem,reg
0001 rrr 0000 mm iii  + sbc    mem,reg
0010 rrr 0000 mm iii  + and    mem,reg
0011 rrr 0000 mm iii  + eor    mem,reg
0100 rrr 0000 mm iii  + ora    mem,reg
0101 rrr 0000 mm iii  + cmp    mem,reg
0110 rrr 0000 mm iii  + load   mem,reg
0111 rrr 0000 mm iii    store  mem,reg
1000 000 nnnn mm iii  * bitset #n,mem
1001 000 nnnn mm iii  * bitclr #n,mem
1010 000 nnnn mm iii  * rol    #n,mem       ; roll left;            n=
0..15
1011 000 nnnn mm iii  * rlc    #n,mem       ; roll left thru carry; n=
1..16
1100 000 nnnn mm iii    addq   #n,mem
1101 rrr nnnn mm iii    bbs    #n,reg,(mem)
1110 rrr nnnn mm iii    bbc    #n,reg,(mem)
1111 000 0000 mm iii    jsr    (mem)
1111 001 0000 00 000    rts
1111 010 0000 00 000    rti
1111 011 0000 mm iii    push   mem
1111 100 0000 mm iii    pop    mem

*) if rrr is non zero, then substitute the low bits of register rrr for
#n
+) if nnnn is non zero, then roll left contents of mem by n before
using


Flags:
carry,zero,negative,interupt-disable,oVerflow. (decimal???)

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shrydar ert jaruth.com
http://www.jaruth.com/shrydar/